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72815LB10BGGI Datasheet(PDF) 8 Page - Integrated Device Technology |
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72815LB10BGGI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 26 page COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18 8 TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE Number of Words in FIFO IDT72805LB IDT72815LB IDT72825LB IDT72845LB FF PAF HF PAE EF 000 0 H H H L L 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HHH L H (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 2,048 HHHHH 129 to (256-(m+1))(2) 257 to (512-(m+1))(2) 513 to (1,024-(m+1))(2) 2,049 to (4,096-(m+1))(2) HH L H H (256-m)to255 (512-m)to511 (1,024-m)to1,023 (4,096-m)to4,095 H L L H H 256 512 1,024 4,096 L L L H H TABLE 2 — STATUS FLAGS FOR FWFT MODE Number of Words in FIFO IDT72805LB IDT72815LB IDT72825LB IDT72845LB IR PAF HF PAE OR 0 000 L H H L H 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) LH H L L (n + 2) to 129 (n + 2) to 257 (n + 2) to 513 (n + 2) to 2,049 L H H H L 130 to (257-(m+1))(2) 258 to (513-(m+1))(2) 514 to (1,025-(m+1))(2) 2,050 to (4,097-(m+1))(2) LH LH L (257-m) to 256 (513-m) to 512 (1,025-m) to 1,024 (4,097-m) to 4,096 LLL H L 257 513 1,025 4,097 H L L H L NOTES: 1. n = Empty offset (Default Values : IDT72805LB n = 31, IDT72815LB n = 63, IDT72825LB/72845LB n = 127) 2. m = Full Offset (Default Values : IDT72805LB m = 31, IDT72815LB m = 63, IDT72825LB/72845LB m = 127) NOTES: 1. n = Empty offset (Default Values : IDT72805LB n=31, IDT72815LB n = 63, IDT72825LB/72845LB n = 127) 2. m = Full offset (Default Values : IDT72805LB m=31, IDT72815LB m = 63, IDT72825LB/72845LB m = 127) onthenextLOW-to-HIGHtransitionofRCLK.ThefirsttransitionofRCLKwill presenttheEmptyOffsetvaluetothedataoutputlines.Thenexttransitionof RCLKwillpresenttheFulloffsetvalue.Offsetregistercontentcanbereadout in the IDT Standard mode only. It cannot be read in the FWFT mode. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM- ING SELECTION TheIDT72805LB/72815LB/72825LB/72845LBcanbeconfiguredduring the"ConfigurationatReset"cycledescribedinTable3witheitherasynchronous or synchronous timing for PAE and PAF flags. If asynchronous PAE/PAF configuration is selected (as per Table 3), the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia- grams, see Figure 13 for asynchronous PAE timing and Figure 14 for asynchronousPAFtiming. IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Fordetail timingdiagrams,seeFigure22forsynchronousPAEtimingandFigure23for synchronousPAFtiming. REGISTER-BUFFERED FLAG OUTPUT SELECTION TheIDT72805LB/72815LB/72825LB/72845LBcanbeconfiguredduring the "Configuration at Reset" cycle described in Table 4 with single, double or tripleregister-bufferedflagoutputsignals.Thevariouscombinationsavailable are described in Table 4 and Table 5. In general, going from single to double ortriplebufferedflagoutputsremovesthepossibilityofmetastableflagindications onboundarystates(i.e,emptyorfullconditions).Thetrade-offistheaddition ofclockcycledelaysfortherespectiveflagtobeasserted.Notallcombinations ofregister-bufferedflagoutputsaresupported.Register-bufferedoutputsapply totheEmptyFlagandFullFlagonly.Partialflagsarenoteffected.Table4and Table5summarizetheoptionsavailable. |
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