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7027S25PFGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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7027S25PFGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 20 page  ©2015 Integrated Device Technology, Inc. AUGUST 2015 DSC 3199/10 1 Functional Block Diagram Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for bus matching capability. ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM IDT7027S/L ◆ ◆ ◆ ◆ ◆ IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V (±10%) power supply ◆ ◆ ◆ ◆ ◆ Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin Ceramic Pin Grid Array (PGA) ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). I/O Control Address Decoder 32Kx16 MEMORY ARRAY 7027 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ WL A14L A0L A14L A0L SEML INTL (2) BUSYL LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/ WR A14R A0R A14R A0R SEMR INTR (2) BUSYR (1,2) LBR R/WR OER UBR M/ S (2) CE1L CE0R CE1R 3199 drw 01 I/O CE1R CE1L 8-15L I/O I/O0-7R I/O8-15R 0-7L R/WL . |
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