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70125L35JG Datasheet(PDF) 11 Page - Integrated Device Technology |
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70125L35JG Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 16 page  11 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges tAPS ADDR 'A' DATAIN'A' MATCH tWC tWP R/ W'A' ADDR'B' DATAOUT 'B' MATCH BUSY'B' tBDA tDW tDH VALID VALID tDDD (4) tWDD tBDD 2654 drw 09 (1) Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3) Timing Waveform of Write with BUSY(3) NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A". NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". 2654 drw 10 R/ W"A" BUSY"B" tWP tWB R/ W"B" tWH (1) (2) , tBDC ADDR"A and B" BUSY"B" CE"A" tAPS (2) tBAC ADDRESSES MATCH CE"B" 2654 drw 11 (1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). |
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