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70125L35JG Datasheet(PDF) 5 Page - Integrated Device Technology |
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70125L35JG Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 16 page 5 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Data Retention Characteristics (L Version Only) Data Retention Waveform AC Test Conditions Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ, tHZ, tWZ, tOW) *Including scope and jig. NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed but is not production tested. VDR 2V ≥ DATA RETENTION MODE Vcc CE 4.5V tCDR tR VIH VDR VIH 4.5V 2654 drw 03 1250 Ω 30pF 775 Ω DATAOUT BUSY INT 5V 5V 1250 Ω 5pF* 775 Ω DATAOUT 2654 drw 04 Symbol Parameter Test Condition Min. Typ.(1) Max. Unit VDR VCC for Data Retention 2.0 ___ ___ V ICCDR Data Retention Current VCC = 2V, CE > VCC - 0.2V IND. ___ 100 4000 µA tCDR(3) Chip Deselect to Data Retention Time VIN > VCC - 0.2V or VIN < 0.2 COM'L. ___ 100 1500 tR(3) Operation Recovery Time tRC(2) ___ ___ V 2654 tbl 07 Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1 and 2 2654 tbl 08 |
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