9

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

MARCH 2013

NOTES:

1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW

during reset will make the pin act as a load enable for the programmable flag offset registers.

2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.

3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.

Figure 4. Reset Timing

RSA (RSB)

RENA1, RENA2

(

RENB1, RENB2)

OEA (OEB) = 1

OEA (OEB) = 0

(2)

EFA, PAEA

(

EFB, PAEB)

FFA, PAFA

(

FFB, PAFB)

3034 drw 05

WENA1

(

WENB1)

WENA2/

LDA

(WENB2/

LDB)

(1)

NOTE:

Figure 5. Write Cycle Timing

WCLKA (WCLKB)

WENA1

(

WENB1)

WENA2 (WENB2)

(If Applicable)

FFA

(

FFB)

RCLKA (RCLKB)

RENA1, RENA2

(

RENB1, RENB2)

NO OPERATION

NO OPERATION

3034 drw 06

DATA IN VALID