10

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

A HIGH on the BE/FWFT input when the Reset (RS1) input goes from

LOW to HIGH will select a Big-Endian arrangement. In this case, the most

significantbyte(word)ofthelongwordwrittentoPortAwillbereadfromPort

Bfirst;theleastsignificantbyte(word)ofthelongwordwrittentoPortAwillbe

read from Port B last.

ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW

toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant

byte (word) of the long word written to Port A will be read from Port B first; the

mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom

Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure

3 (Reset) for an Endian select timing diagram.

— TIMING MODE SELECTION

AfterReset, theFWFTselectfunctionisactive,permittingachoicebetween

two possible timing modes: IDT Standard mode or First Word Fall Through

(FWFT)mode. OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT

inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT

Standard mode. This mode uses the Empty Flag function (EF) to indicate

whether or not there are any words present in the FIFO memory. It uses the

FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree

space for writing. In IDT Standard mode, every word read from the FIFO,

includingthefirst,mustberequestedusingaformalreadoperation.

OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring

thenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectFWFTmode.

ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere

isvaliddataatthedataoutputs(B0-B35). ItalsousestheInputReadyfunction

(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata

outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessedby

performingaformalreadoperation.

Following Reset, the level applied to the BE/FWFT input to choose the

desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto

Figure 3 (Reset) for a First Word Fall Through select timing diagram.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Two registers in the IDT723623/723633/723643 are used to hold the

offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag

(AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled

Y.Theoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofthe

FIFO, programmed in parallel using the FIFO’s Port A data inputs, or

programmedinserialusingtheSerialData(SD)input(seeTable1).SPM,FS0/

SD and FS1/SEN function the same way in both IDT Standard and FWFT

modes.

— PRESET VALUES

ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters

withoneofthethreepresetvalueslistedinTable1,theSerialProgramMode

(SPM)andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-

to-HIGH transition of the Reset input (RS1). For example, to load the preset

valueof64intoXandY,SPM,FS0andFS1mustbeHIGHwhenRS1returns

HIGH. For the relevant preset value loading timing diagram, see Figure 3.

SIGNAL DESCRIPTION

RESET (RS1/RS2)

Afterpowerup,aResetoperationmustbeperformedbyprovidingaLOW

pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the

IDT723623/723633/723643 undergoes a complete reset by taking its Reset

(RS1 and RS2) input LOW for at least four Port A clock (CLKA) and four Port

B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch

asynchronously to the clocks. A Reset initializes the internal read and write

pointersandforcestheFull/InputReadyflag(FF/IR)LOW,theEmpty/Output

Readyflag(EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost-

Fullflag(AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe

parallelmailboxregisterHIGH,andatthesametimetheRS2andMBF2operate

likewise. AfteraReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwo

writeclockcyclestobeginnormaloperation.

ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue

of the Big-Endian (BE) input for determining the order by which bytes are

transferredthroughPortB.

ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputalsolatchesthe

values of the Flag Select (FS0, FS1) and Serial Programming Mode (SPM)

inputs for choosing the Almost-Full and Almost-Empty offset programming

method (for details see Table 1, Flag Programming, and Almost-Empty and

Almost-Fullflagoffsetprogramming section).TherelevantReset timingdiagram

can be found in Figure 3.

PARTIAL RESET (PRS)

The FIFO memory of the IDT723623/723633/723643 undergoes a

limitedresetbytakingitsassociatedPartialReset(PRS)inputLOWforatleast

fourPortAclock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.

ThePartialResetinput canswitchasynchronouslytotheclocks. APartialReset

initializestheinternalreadandwritepointersandforcestheFull/InputReady

flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost-

Emptyflag(AE)LOW,andtheAlmost-Fullflag(AF)HIGH. APartialResetalso

forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH.

AfteraPartialReset,theFIFO’sFull/InputReadyflagissetHIGHaftertwoclock

cycles to begin normal operation. See Figure 4, Partial Reset (IDTStandard

and FWFT Modes) for the relevant timing diagram.

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedat thetimeaPartial

Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof

the reset operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Reset would be inconvenient.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionis

active,permittingachoiceofBig-orLittle-Endianbytearrangementfordataread

fromPortB. Thisselectiondeterminestheorderbywhichbytes(orwords)of

dataaretransferredthroughthisport. Forthefollowingillustrations,assumethat

a byte (or word) bus size has been selected for Port B. (Note that when Port

Bisconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication

NOTE:

1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused

inputs) must not be left open, rather they must be either HIGH or LOW.