72220L25TPG datasheet(4/11 Pages) IDT

Part #	72220L25TPG

Description	CMOS SyncFIFO

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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COMMERCIALTEMPERATURERANGE

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0

°C to + 70°C)

Commercial

IDT72420L10

IDT72420L15

IDT72420L25

IDT72200L10

IDT72200L15

IDT72200L25

IDT72210L10

IDT72210L15

IDT72210L25

IDT72220L10

IDT72220L15

IDT72220L25

IDT72230L10

IDT72230L15

IDT72230L25

IDT72240L10

IDT72240L15

IDT72240L25

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

100

—

66.7

—

40

MHz

tA

DataAccessTime

2

6.5

2

10

2

15

ns

tCLK

Clock Cycle Time

10

—

15

—

25

—

ns

tCLKH

Clock High Time

4.5

—

6

—

10

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

10

—

ns

tDS

DataSetupTime

3

—

4

—

6

—

ns

tDH

DataHoldTime

0.5

—

1

—

1

—

ns

tENS

EnableSetupTime

3

—

4

—

6

—

ns

tENH

EnableHoldTime

0.5

—

1

—

1

—

ns

tRS

ResetPulseWidth(1)

10

—

15

—

15

—

ns

tRSS

ResetSetupTime

8

—

10

—

15

—

ns

tRSR

Reset Recovery Time

8

—

10

—

15

—

ns

tRSF

ResettoFlagandOutputTime

—

10

—

15

—

25

ns

tOLZ

OutputEnabletoOutputinLow-Z(2)

0

—

0—

ns

tOE

OutputEnabletoOutputValid

2

6

3

8

3

13

ns

tOHZ

OutputEnabletoOutputinHigh-Z(2)

2

6

383

13

ns

tWFF

Write Clock to Full Flag

—

6.5

—

10

—

15

ns

tREF

Read Clock to Empty Flag

—

6.5

—

10

—

15

ns

tAF

Write Clock to Almost-Full Flag

—

6.5

—

10

—

15

ns

tAE

Read Clock to Almost-Empty Flag

—

6.5

—

10

—

15

ns

tSKEW1

Skew time between Read Clock & Write Clock for

4

—

6

—

10

—

ns

Empty Flag & Full Flag

tSKEW2

Skew time between Read Clock & Write Clock for

10

—

15

—

18

—

ns

Almost-Empty Flag & Almost-Full Flag

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

or equivalent circuit

Figure 1. Output Load

*Includes jig and scope capacitances.

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

Symbol

Parameter

Conditions

Max.

Unit

CIN

Input Capacitance

VIN = 0V

10

pF

COUT

Output Capacitance

VOUT = 0V

10

pF

(1, 2)

(2)

NOTES:

1. With output deselected. (OE

≥ VIH)

2. Characterized values, not currently tested.

AC TEST CONDITIONS

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

30pF*

1.1K

Ω

5V

680

Ω

D.U.T.

2680 drw03

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