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723633L12PFG Datasheet(PDF) 11 Page - Integrated Device Technology |
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723633L12PFG Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 28 page  11 COMMERCIALTEMPERATURERANGE IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 TABLE 1 — FLAG PROGRAMMING SPM FS1/SEN FSO/SD RS1 X AND Y REGlSTERS(1) HH H ↑ 64 HH L ↑ 16 HL H ↑ 8 HL L ↑ Parallel programming via Port A LH L ↑ Serial Programming via SD LH H ↑ reserved LL H ↑ reserved LL L ↑ reserved NOTE: 1. X register holds the offset for AE; Y register holds the offset for AF. — PARALLEL LOAD FROM PORT A To program the X and Y registers from Port A, perform a Reset on with SPMHIGHandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1. Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredatain RAM. The first two write cycles load the offset registers in the order Y, X. On thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure 5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT modes), for a detailed timingdiagram.ThePortAdatainputsusedbytheoffsetregistersare(A7-A0), (A8-A0), or (A9-A0) for the IDT723623, IDT723633 or IDT723643, respec- tively. Thehighestnumberedinputisusedasthemostsignificantbitofthebinary numberineachcase. Validprogrammingvaluesfortheregistersrangefrom 1 to 252 for the IDT723623; 1 to 508 for the IDT723633; and 1 to 1,020 for the IDT723643. AfteralltheoffsetregistersareprogrammedfromPortAtheFIFO beginsnormaloperation. — SERIAL LOAD ToprogramtheXandYregistersserially,initiateaResetwithSPMLOW, FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. There are 16-, 18- or 20-bit writes are needed to complete the programming for the IDT723623, IDT723633, or IDT723643, respectively. ThetworegistersarewrittenintheorderY,X.Eachregistervalue CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O PORT FUNCTION H X X X X High-Impedance None L H L X X Input None LH H L ↑ Input FIFO write LH H H ↑ Input Mail1write L L L L X Output None LL H L ↑ Output None L L L H X Output None LL H H ↑ Output Mail2 read (set MBF2 HIGH) TABLE 2 — PORT A ENABLE FUNCTION TABLE TABLE 3 — PORT B ENABLE FUNCTION TABLE CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O PORT FUNCTION H X X X X High-Impedance None L L L X X Input None LL H L ↑ Input None LL H H ↑ Input Mail2write L H L L X Output None LH H L ↑ Output FIFO read L H L H X Output None LH H H ↑ Output Mail1 read (set MBF1 HIGH) |
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