4

COMMERCIALTEMPERATURERANGE

IDT723623/723633/723643 BUS-MATCHING SyncFIFO™

256 x 36, 512 x 36, 1,024 x 36

PIN DESCRIPTIONS

Symbol

Name

I/O

Description

A0-A35

Port A Data

I/O

36-bitbidirectionaldataportforsideA.

AE

Almost-Empty

O

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the FIFO

Flag (Port B)

is less than or equal to the value in the Almost-Empty B offset register, X.

AF

Almost-Full

O

ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsinthe

Flag (Port A)

FIFO is less than or equal to the value in the Almost-Full A offset register, Y.

B0-B35

Port B Data

I/O

36-bitbidirectionaldataportforsideB.

BE/FWFT

Big-Endian/

I

This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case,

FirstWord

depending on the bus size, the most significant byte or word written to Port A is read from Port B first. A

Fall Through

LOW on BE will select Little-Endian operation. In this case, the least significant byte or word written to Port A

is read from Port B first. After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT

Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the

level on FWFT must be static throughout device operation.

Bus-Match

I

A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A

Select(PortB)

LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian

arrangement for Port B. The level of BM must be static throughout device operation.

CLKA

Port A Clock

I

CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or

coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH transition of CLKA.

CLKB

Port B Clock

I

CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or

coincident to CLKA. EF/OR and AE are synchronized to the LOW-to-HIGH transition of CLKB.

CSA

Port A Chip

I

CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

Select

outputs are in the high-impedance state when CSA is HIGH.

CSB

Port B Chip

I

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35

Select

outputs are in the high-impedance state when CSB is HIGH.

EF/OR

Empty/Output

O

This is a dual function pin. In the IDT Standard mode, the EF function is selected. EF indicates whether or

Ready Flag

nottheFIFOmemoryisempty. IntheFWFTmode,theORfunctionisselected.ORindicatesthepresenceofvalid

(Port B)

dataontheB0-B35outputs,availableforreading.EF/ORissynchronizedtotheLOW-to-HIGHtransitionofCLKB.

ENA

Port A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.

ENB

Port B Enable

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.

FF/IR

Full/Input

O

This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates whether or

Ready Flag

not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there

(Port A)

is space available for writing to the FIFO memory. FF/IR is synchronized to the LOW-to-HIGH transition of

CLKA.

FS1/SEN

FlagOffset

I

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Reset,

Select1/

FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister

SerialEnable,

programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel

load from Port A, and serial load.

FS0/SD

FlagOffset

I

When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous

Select0/

to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present

SerialData

on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16

for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register

MSB and the last bit write stores the X-register LSB.

MBA

Port A Mailbox

I

A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.

Select

MBB

Port B Mailbox

I

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35

Select

outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level

selectsFIFOdataforoutput.

MBF1

Mail1Register

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to

Flag

the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB

when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Reset (RS1) or Partial

Reset (PRS).