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723633L12PFG8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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723633L12PFG8 Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 28 page  3 COMMERCIALTEMPERATURERANGE IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset is useful since it permits flushing of the FIFO memory without changing any configurationsettings. Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstword written to an empty FIFO appears automatically on the outputs, no read operationrequired(Nevertheless,accessingsubsequentwordsdoesneces- sitate a formal read request). The state of the BE/FWFT pin during Reset determinesthemodeinuse. The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a combinedFull/InputReadyFlag(FF/IR). TheEFandFFfunctionsareselected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions areselectedintheFirstWordFallThroughmode. IRindicateswhetherornot theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata availableforreadingornot. Itmarksthepresenceofvaliddataontheoutputs. TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram- mable Almost-Full flag (AF). AE indicates when a selected number of words remainin theFIFOmemoryachieveapredetermined"almost-emptystate". AFindicateswhentheFIFOcontainsmorethanaselectednumberofwords. FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata intoitsarray.EF/ORandAEaretwo-stagesynchronizedtotheportclockthat readsdatafromitsarray. ProgrammableoffsetsforAEandAF areloaded in parallelusingPortAorinserialviatheSDinput.TheSerialProgrammingMode pin(SPM)makesthisselection.Threedefaultoffsetsettingsarealsoprovided. TheAEthresholdcanbesetat8,16or64locationsfromtheemptyboundary andtheAFthresholdcanbesetat8,16or64locationsfromthefullboundary. All these choices are made using the FS0 and FS1 inputs during Reset. Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths. InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin seriestocreategreaterworddepths. Theadditionofexternalcomponentsis unnecessary. If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill automatically power down. During the power down state, supply current consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol inputs)willimmediatelytakethedeviceoutofthePowerDownstate. TheIDT723623/723633/723643arecharacterizedforoperationfrom0 °C to70 °C.Theyarefabricatedusinghighspeed,submicronCMOStechnology. |
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