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70261L35PFG8 Datasheet(PDF) 2 Page - Integrated Device Technology |
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70261L35PFG8 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 20 page 6.42 IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Industrial and Commercial Temperature Ranges 2 Pin Configurations(1,2,3) Pin Names NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Description The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT70261isdesignedtobeusedasastand-aloneDual-PortRAMoras acombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-moreword systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin32- bitorwidermemorysystemapplicationsresultsinfull-speed,error-free operationwithouttheneedforadditionaldiscretelogic. This device provides two independent ports with separate control, address,andI/Opinsthatpermitindependent,asynchronousaccessfor reads or writes to any location in memory. An automatic power down featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter a very low standby power mode. Fabricated using CMOS high-performance technology, these de- vices typically operate on only 750mW of power. The IDT70261 is packaged in a 100-pin TQFP. Index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 9291 9089 8887 86 85 8483 82 8180 79 78 77 76 N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R I/O6R N/C N/C N/C N/C 3039 drw 02 N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL GND M/ S BUSYR INTR A0R N/C N/C N/C BUSYL A1R A2R A3R A4R IDT70261PF PN100(4) 100-Pin TQFP Top View(5) A6L A5R Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3039 tbl 01 |
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