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70121S55JGI Datasheet(PDF) 8 Page - Integrated Device Technology |
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70121S55JGI Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 16 page  6.42 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges 8 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA . 4. 'X' in part numbers indicates power rating (S or L). 5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW. 6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Symbol Parameter 70121X25 70125X25 Com'l Only 70121X35 70125X35 Com'l & Ind Unit Min. Max. Min. Max. WRITE CYCLE tWC Write Cycle Time (4) 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width(6) 20 ____ 30 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 12 ____ 20 ____ ns tHZ Output High-Z Time(1,2,3) ____ 10 ____ 15 ns tDH Data Hold Time(5) 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,3) ____ 10 ____ 15 ns tOW Output Active from End-of-Write(1,2,3,5) 0 ____ 0 ____ ns 2654 tbl 10a Symbol Parameter 70121X55 70125X55 Com'l Only Unit Min. Max. WRITE CYCLE tWC Write Cycle Time(4) 55 ____ ns tEW Chip Enable to End-of-Write 40 ____ ns tAW Address Valid to End-of-Write 40 ____ ns tAS Address Set-up Time 0 ____ ns tWP Write Pulse Width(6) 40 ____ ns tWR Write Recovery Time 0 ____ ns tDW Data Valid to End-of-Write 20 ____ ns tHZ Output High-Z Time(1,2,3) ____ 30 ns tDH Data Hold Time(5) 0 ____ ns tWZ Write Enable to Output in High-Z(1,3) ____ 30 ns tOW Output Active from End-of-Write(1,2,3,5) 0 ____ ns 2654 tbl 10b |
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