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7024L15JGB8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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7024L15JGB8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 22 page  1 ©2013 Integrated Device Technology, Inc. JUNE 2013 DSC 2740/14 IDT7024S/L HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM ◆ ◆ ◆ ◆ ◆ IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/ S = H for BUSY output flag on Master M/ S = L for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ Battery backup operation—2V data retention ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V (±10%) power supply ◆ ◆ ◆ ◆ ◆ Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Quad Flatpack ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts availble, see ordering information Functional Block Diagram Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL BUSYL A11L A0L 2740 drw 01 UBL LBL CEL OEL I/O8L-I/O15L I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/ S R/ WR BUSYR UBR LBR CER OER I/O8R-I/O15R I/O0R-I/O7R A11R A0R R/ WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 12 12 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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