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723622L15PFG8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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723622L15PFG8 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 24 page 8 IDT723622/723632/723642 CMOS SyncBiFIFO™ 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIALTEMPERATURERANGE NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF (Commercial: VCC = 5V ± 10%, TA = 0 °C to +70°C) Commercial IDT723622L15 IDT723632L15 IDT723642L15 Symbol Parameter Min. Max. Unit tA Access Time, CLKA ↑ to A0-A35 and CLKB↑ to B0-B35 2 10 ns tPIR Propagation Delay Time, CLKA ↑ to IRA and CLKB↑ to IRB 2 8 ns tPOR Propagation Delay Time, CLKA ↑ to ORA and CLKB↑ to ORB 1 8 ns tPAE Propagation Delay Time, CLKA ↑ to AEA and CLKB↑ to AEB 18 ns tPAF Propagation Delay Time, CLKA ↑ to AFA and CLKB↑ to AFB 18 ns tPMF Propagation Delay Time, CLKA ↑ to MBF1 LOW or MBF2 HIGH and 0 8 ns CLKB ↑ to MBF2 LOW or MBF1 HIGH tPMR Propagation Delay Time, CLKA ↑ to B0-B35(1) and CLKB↑ to A0-A35(2) 210 ns tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 10 ns tRSF Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and 1 15 ns MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW 2 10 ns and W/RB HIGH to B0-B35 Active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and 1 8 ns CSB HIGH or W/RB LOW to B0-B35 at high-impedance |
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