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IDT723626 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT723626 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 35 page  1 JULY 2014 IDT723626 IDT723636 IDT723646 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3271/6 © CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIALTEMPERATURERANGE FUNCTIONAL BLOCK DIAGRAM FEATURES: ••••• Memory storage capacity: IDT723626 – 256 x 36 x 2 IDT723636 – 512 x 36 x 2 IDT723646 – 1,024 x 36 x 2 ••••• Clock frequencies up to 67 MHz (10ns access time) ••••• Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) ••••• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C ••••• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) ••••• Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64) ••••• Serial or parallel programming of partial flags ••••• Big- or Little-Endian format for word and byte bus sizes ••••• Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings ••••• Mailbox bypass registers for each FIFO ••••• Free-running CLKA, CLKB and CLKC may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ••••• Auto power down minimizes power dissipation ••••• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) ••••• Green parts available, see ordering information DESCRIPTION: TheIDT723626/723636/723646isamonolithic,high-speed,low-power, CMOSTripleBussynchronous(clocked)FIFOmemorywhichsupportsclock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two Mail 1 Register Programmable Flag Offset Registers RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Write Pointer Read Pointer Status Flag Logic RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Write Pointer Read Pointer Status Flag Logic CLKA CSA W/ RA ENA MBA Port-A Control Logic FIFO1, Mail1 Reset Logic MRS1 Mail 2 Register MBF2 WENC Port-C Control Logic FIFO2, Mail2 Reset Logic MRS2 MBF1 FIFO1 FIFO2 10 EFB/ORB AEB 18 18 FFC/IRC AFC B0-B17 FFA/IRA AFA SPM FS0/SD FS1/ SEN A0-A35 EFA/ORA AEA 3271 drw01 36 36 PRS2 PRS1 Timing Mode FWFT C0-C17 CLKB Port-B Control Logic Common Port Control Logic (B and C) BE SIZEB SIZEC CLKC MBC 36 36 36 36 RENB MBB CSB |
Similar Part No. - IDT723626_14 |
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Similar Description - IDT723626_14 |
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