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7035L20PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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7035L20PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 19 page  ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC 4088/10 1 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/WL BUSYL A12L A0L 4088 drw 01 UBL LBL CEL OEL I/O9L-I/O17L I/O0L-I/O8L CEL OEL R/WL SEML INTL M/S R/WR BUSYR UBR LBR CER OER I/O9R-I/O17R I/O0R-I/O8R A12R A0R R/WR SEMR INTR CER OER (2) (1,2) (1,2) (2) 13 13 IDT7035S/L HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7035S Active: 800mW (typ.) Standby: 5mW (typ.) – IDT7035L Active: 800mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ IDT7035 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ Battery backup operation—2V data retention ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 5V (±10%) power supply ◆ ◆ ◆ ◆ ◆ Available in 100-pin Thin Quad Flatpack Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available. See ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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