6.42

IDT7034S/L

High-Speed 4K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

9

NOTES:

1. R/W or CE or UB & LB must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

UB or LB

4089 drw 07

(9)

CE or SEM

(9)

(7)

(3)

4089 drw 08

ADDRESS

R/

W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)