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7038L15PFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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7038L15PFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  1 ©2015 Integrated Device Technology, Inc. FEBRUARY 2015 DSC-4837/5 I/O Control Address Decoder 64Kx18 MEMORY ARRAY 7038 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ WL A15L A0L SEML INTL (2) BUSYL (1,2) LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/ WR A15R A0R SEMR INTR (2) BUSYR (1,2) LBR R/WR OER UBR M/ S (1) CE1L CE0R CE1R 4837 drw 01 CE1R CE1L I/O 9-17L I/O9-17R I/O 0-8L R/WL . 16 16 I/O0-8R Functional Block Diagram ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ Separate upper-byte and lower-byte controls for multi- plexed bus and bus matching compatibility ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in a 100-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) ◆ Low-power operation – IDT7038L Active: 1W (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT7038 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 64K x 18 DUAL-PORT STATIC RAM IDT7038L NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). |
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