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7027L15GGI8 Datasheet(PDF) 11 Page - Integrated Device Technology |
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7027L15GGI8 Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 20 page 6.42 IDT7027S/L High-Speed 32K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 Timing Waveform of Semaphore Read after Write Timing, Either Side(1) Timing Waveform of Semaphore Write Contention(1,3,4) NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table. 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. SEM 3199 drw 09 tAW tEW tSOP I/O0 VALID ADDRESS tSAA R/ W tWR tOH tACE VALID ADDRESS DATAIN VALID DATAOUT tDW tWP tDH tAS tSWRD tAOE Read Cycle Write Cycle A0-A2 OE VALID(2) SEM"A" 3199 drw 10 tSPS MATCH R/ W"A" MATCH A0"A"-A2"A" SIDE "A" (2) SEM"B" R/ W"B" A0"B"-A2"B" SIDE (2) "B" |
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