MEGAWIN

MLC852P Technical Summary

7

Dividers

Divider0 is a 7-bit up-counter. The clock source is from Fosc. It could be reset to 00H by POR,

system reset or waked from stop mode. Certain intermediary signals of the divider 0 could be the

clock source of timer0.

Divider 0

Fosc

Fosc

Fosc/2

Fosc/4

Fosc/32

Fosc/128

timer 0

TM0X

P0.5

Divider1:

Divider1 is a 14-bit up-counter. The clock source is from sub-oscillator (32 KHz). It could be reset to

0000H by POR, system reset or waked from stop mode. DIV1x_sel could select the source of

interrupt.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

1203H

DIV1x_SEL

-

-

-

-

-

-

CKO1

CKO0

√

√

CKO1

CKO0

Selected DIV1x frequency

0

0

0

1

1

0

1

1

unused

Divider 1

2Hz

128Hz

512Hz

4096Hz

DIV1X_SEL

DIV1X

2HzX