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70V06L20JG Datasheet(PDF) 3 Page - Integrated Device Technology |
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70V06L20JG Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 23 page 6.42 IDT70V06S/L High-Speed 3.3V 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 3 Pin Names NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 1.18 in x 1.18 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. Pin Configurations(1,2,3) (con't.) 2942 drw 04 51 50 48 46 44 42 40 38 36 53 55 57 59 61 63 65 67 68 66 13 57 9 11 13 15 20 22 24 26 28 30 32 35 IDT70V06G G68(4) 68-Pin PGA Top View(5) AB C D EF G H J K L 47 45 43 41 34 21 23 25 27 29 31 33 24 68 10 12 14 16 18 19 17 56 58 60 62 64 11 10 09 08 07 06 05 04 03 02 01 52 54 49 39 37 A5L INTL N/C SEML CEL VDD OEL R/ WL I/O0L N/C VSS VSS I/O0R VDD N/C OER R/ WR SEMR CER VSS BUSYR BUSYL M/S INTR N/C VSS A1R A13L A13R INDEX A4L A2L A0L A3R A2R A4R A5R A7R A6R A9R A8R A11R A10R A12R A0R A7L A6L A3L A1L A9L A8L A11L A10L A12L VDD I/O2R I/O3R I/O5R I/O6R I/O1R I/O4R I/O7R I/O1L I/O2L I/O4L I/O7L I/O3L I/O5L I/O6L Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VDD Power (3.3V) VSS Ground (0V) 2942 tbl 01 |
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