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72V235L20PFGI Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 72V235L20PFGI
Description  3.3 VOLT CMOS SyncFIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72V235L20PFGI Datasheet(HTML) 11 Page - Integrated Device Technology

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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 5. Reset Timing(2)
Figure 6. Write Cycle Timing with Single Register-Buffered FF
FF
FF
FF
FF (IDT Standard Mode)
WCLK
D0 - D17
WEN
FF
tCLK
tCLKH
tCLKL
tDS
tENS
tDH
tENH
tWFF
tWFF
DATA IN VALID
NO OPERATION
RCLK
tSKEW1
(1)
REN
4294 drw 06
RS
REN, WEN, LD
PAE
PAF, WXO/
HF, RXO
Q0 - Q17
OE = 0
OE = 1
(1)
4294 drw 05
tRSS
CONFIGURATION SETTING
tRSR
FL, RXI, WXI
RCLK, WCLK
FF/IR
EF/OR
FWFT Mode
IDT Standard Mode
(3)
(2)
tRSF
tRSF
tRSF
tRSF
tRSF
tRSR
tRS
FWFT Mode
IDT Standard Mode
(4)
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
4. In FWFT mode IR goes LOW based on the WCLK edge after Reset.


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