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7008S55GG8 Datasheet(PDF) 5 Page - Integrated Device Technology |
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7008S55GG8 Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 20 page 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 5 Truth Table I: Chip Enable(1) Truth Table II: Non-Contention Read/Write Control NOTES: 1. A0L – A15L ≠ A0R – A15R. 2. Refer to Chip Enable Truth Table. Truth Table III: Semaphore Read/Write Control(1) NOTES: 1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2. 2. Refer to Chip Enable Truth Table. NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. CE CE0 CE1 Mode L VIL VIH Port Selected (TTL Active) < 0.2V >VCC -0.2V Port Selected (CMOS Active) H VIH X Port Deselected (TTL Inactive) XVIL Port Deselected (TTL Inactive) >VCC -0.2V X Port Deselected (CMOS Inactive) X<0.2V Port Deselected (CMOS Inactive) 3198 tbl 02 Inputs(1) Outputs Mode CE(2) R/W OE SEM I/O0-7 H X X H High-Z Deselected: Power-Down LL X H DATAIN Write to memory LH LH DATAOUT Read memory X X H X High-Z Outputs Disabled 3198 tbl 03 Inputs Outputs Mode CE(2) R/W OE SEM I/O0-7 HH L L DATAOUT Read Semaphore Flag Data Out H ↑ XL DATAIN Write I/O0 into Semaphore Flag LX X L ______ Not Allowed 3198 tbl 04 |
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