72V841L15PFGI datasheet(5/16 Pages) IDT

Part #	72V841L15PFGI

Description	3.3 VOLT DUAL CMOS SyncFIFO

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Manufacturer	IDT [Integrated Device Technology]

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IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM

DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

In Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

InputTimingReferenceLevels

1.5V

OutputReferenceLevels

1.5V

OutputLoad

See Figure 1

Commercial

Com’l & Ind’l

Commercial

IDT72V801L10

IDT72V801L15

IDT72V801L20

IDT72V811L10

IDT72V811L15

IDT72V811L20

IDT72V821L10

IDT72V821L15

IDT72V821L20

IDT72V831L10

IDT72V831L15

IDT72V831L20

IDT72V841L10

IDT72V841L15

IDT72V841L20

IDT72V851L10

IDT72V851L15

IDT72V851L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

100

—

66.7

—

50

MHz

tA

Data Access Time

2

6.5

2

10

2

12

ns

tCLK

Clock Cycle Time

10

—

15(1)

—20

—

ns

tCLKH

Clock High Time

4.5

—

6

—

8

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

8

—

ns

tDS

DataSet-upTime

3

—

4

—

5

—

ns

tDH

Data Hold Time

0.5

—

1

—

1

—

ns

tENS

EnableSet-upTime

3

—

4

—

5

—

ns

tENH

Enable Hold Time

0.5

—

1

—

1

—

ns

tRS

Reset Pulse Width(2)

10

—

15

—

20

—

ns

tRSS

ResetSet-upTime

8

—

10

—

12

—

ns

tRSR

Reset Recovery Time

8

—

10

—

12

—

ns

tRSF

Reset to Flag Time and Output Time

—

10

—

15

—

20

ns

tOLZ

Output Enable to Output in Low-Z(3)

0—

0

—

0—

ns

tOE

Output Enable to Output Valid

3

6

3

8

3

10

ns

tOHZ

Output Enable to Output in High-Z(3)

363

8

3

10

ns

tWFF

Write Clock to Full Flag

—

6.5

—

10

—

12

ns

tREF

Read Clock to Empty Flag

—

6.5

—

10

—

12

ns

tPAF

Write Clock to Programmable Almost-Full Flag

—

6.5

—

10

—

12

ns

tPAE

Read Clock to Programmable Almost-Empty Flag

—

6.5

—

10

—

12

ns

tSKEW1

Skew Time Between Read Clock and Write Clock

5

—

6

—

8

—

ns

for Empty Flag and Full Flag

tSKEW2

Skew Time Between Read Clock and Write Clock for

14

—

18

—

20

—

ns

ProgrammableAlmost-EmptyFlagandProgrammable

Almost-FullFlag

*Includes jig and scope capacitances.

Figure 1. Output Load

or equivalent circuit

NOTES:

1. Industrial temperature range product for the 15ns speed grade is available as a standard device.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

30pF*

330

Ω

3.3V

510

Ω

D.U.T.

4093 drw 03

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 3.3V ± 0.3V, TA = 0

°C to +70°C; Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)

AC TEST CONDITIONS

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