Electronic Components Datasheet Search |
|
72V811L10PFGI Datasheet(PDF) 6 Page - Integrated Device Technology |
|
72V811L10PFGI Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 16 page 6 IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES LDA WENA1 WCLKA OPERATION ON FIFO A LDB WENB1 WCLKB OPERATION ON FIFO B 0 0 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 NoOperation 1 0 Write Into FIFO 1 1 NoOperation Figure 2. Writing to Offset Registers for FIFOs A and B When either of the two Read Enable, RENA1, RENA2 (RENB1, RENB2) associatedwithFIFOA(B)isHIGH,theoutputregisterholdsthepreviousdata and no new data is allowed to be loaded into the register. When all the data has been read from FIFO A (B), the Empty Flag, EFA (EFB) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, EFA(EFB) will go HIGH after tREF and a valid read can begin. The Read Enables, RENA1, RENA2(RENB1, RENB2) are ignored when FIFO A (B) is empty. Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is enabled(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheir respective output register. When Output Enable, OEA (OEB) is disabled (HIGH), the QA (QB) output data bus is in a high-impedance state. Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual- purpose pin. FIFO A (B) is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If WENA2/LDA (WENB2/LDB) issetHIGHatReset,RSA=LOW(RSB=LOW),thispinoperates as a second Write Enable pin. If FIFO A (B) is configured to have two write enables, when Write Enable 1,WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacan beloadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition ofeveryWriteClock,WCLKA(WCLKB). Dataisstoredinthearraysequentially and independently of any on-going read operation. Inthisconfiguration,whenWENA1(WENB1)isHIGHand/orWENA2/LDA (WENB2/LDB) is LOW, the input register of Array A holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag, FFA(FFB) will go LOW, inhibiting furtherwriteoperations. Uponthecompletionofavalidreadcycle,FFA(FFB) willgoHIGHaftertWFF,allowingavalidwritetobegin. WENA1,(WENB1)and WENA2/LDA(WENB2/LDB) are ignored when the FIFO is full. FIFO A (B) is configured to have programmable flags when the WENA2/ LDA(WENB2/LDB)issetLOWatReset,RSA = LOW(RSB = LOW). EachFIFO SIGNAL DESCRIPTIONS FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond- ing signal names for FIFO B are provided in parentheses. INPUTS: Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs for memory array A. DB0 - DB8 are the nine data inputs for memory array B. CONTROLS: Reset(RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA (RSB) input is taken to a LOW state. During reset, the internal read and write pointersassociatedwiththeFIFOaresettothefirstlocation.Aresetisrequired after power-up before a write operation can take place. The Full Flag, FFA (FFB)andProgrammableAlmost-FullFlag,PAFA(PAFB)willberesettoHIGH aftertRSF. TheEmptyFlag,EFA(EFB)andProgrammableAlmost-EmptyFlag, PAEA(PAEB)willberesettoLOWaftertRSF. Duringreset,theoutputregister is initialized to all zeros and the offset registers are initialized to their default values. WriteClock(WCLKA,WCLKB)—AwritecycletoArrayA(B)isinitiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold times must be met with respect to the LOW-to-HIGH transition of WCLKA (WCLKB). The Full Flag, FFA (FFB) and Programmable Almost-Full Flag, PAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionof theWriteClock,WCLKA(WCLKB). The Write and Read clock can be asynchronous or coincident. Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for programmable flags, WENA1(WENB1) is the only enable control pin. In this configuration,whenWENA1(WENB1)isLOW,datacanbeloadedintotheinput register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock, WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently of any on-going read operation. In this configuration, when WENA1 (WENB1) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth expansion. See Write Enable 2 paragraph below for operation in this configuration. To prevent data overflow, FFA(FFB) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the FFA(FFB) will go HIGH after tWFF, allowing a valid write to begin. WENA1(WENB1) is ignored when FIFO A (B) is full. Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag, EFA (EFB)andProgrammableAlmost-EmptyFlag,PAEA(PAEB)aresynchronized with respect to the LOW-to-HIGH transition of RCLKA (RCLKB). The Write and Read Clock can be asynchronous or coincident. Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read Enables, RENA1, RENA2(RENB1, RENB2) are LOW, data is read from Array A(B)totheoutputregisterontheLOW-to-HIGHtransitionoftheReadClock, RCLKA (RCLKB). NOTE: 4093 tbl 08 1. For the purposes of this table, WENA2 and WENB2 = VIH. 2. The same selection sequence applies to reading from the registers. RENA1 and RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-HIGH transition of RCLKA (RCLKB). |
Similar Part No. - 72V811L10PFGI |
|
Similar Description - 72V811L10PFGI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |