 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
72V2113L7-5PFG Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
72V2113L7-5PFG Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 46 page  3 IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or a 9-bit width as determined by the state ofexternalcontrolpinsInputWidth(IW)andOutputWidth(OW)duringtheMaster Resetcycle. TheinputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the input port is controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR, theWENinputshouldbetiedtoitsactivestate,(LOW). TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface, or Asynchronous interface. During Synchronous operation the output port is controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe FIFO. Data is read on a rising edge of RD, the REN input should be tied to its activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport the FIFO must be configured for Standard IDT mode, and the OE input used toprovidethree-statecontroloftheoutputs,Qn. ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0 tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency of the one clock input with respect to the other. Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. In FWFT mode, the first word written to an empty FIFO is clocked directly tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes PIN CONFIGURATIONS (CONTINUED) BGA: 1mm pitch, 11mm x 11mm (BC100, order code: BC) TOP VIEW ASYW WEN WCLK PAF FF/IR BE ASYR PFM RM REN SEN MRS PRS LD HF FSEL0 IP PAE EF/OR RCLK FWFT/SI OW VCC VCC VCC RT OE D17 IW VCC GND GND GND GND VCC Q16 Q17 D16 D13 VCC GND Q15 D15 D14 VCC GND Q12 D11 D12 VCC GND Q10 D8 D9 D10 VCC Q8 D6 D7 D2 D0 Q7 D5 D4 D3 D1 TRST TDI Q0 Q3 Q5 Q6 A1 BALL PAD CORNER A B C D E F G H J K 12 3 4 5 6 7 8 9 10 6119 drw02b GND GND GND VCC Q14 GND GND GND VCC Q13 Q9 GND GND GND VCC Q11 TMS TCK TDO Q2 Q4 VCC VCC VCC Q1 VCC VCC FSEL1 DESCRIPTION (CONTINUED) |
Similar Part No. - 72V2113L7-5PFG |
|
Similar Description - 72V2113L7-5PFG |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
