6.42

IDT7015S/L

High-Speed 8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

R/

W

(2)

OE

ADDRESS

CE or SEM

(6)

(4)

(4)

(3)

2954 drw 09

(7)

(9)

(7)

,

(7)

2954 drw 10

ADDRESS

CE or SEM

R/

W

(3)

(2)

(6)

(9)