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72V36110L6PFG Datasheet(PDF) 7 Page - Integrated Device Technology |
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72V36110L6PFG Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 48 page  7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 43-47 and Figures 31-33. PIN DESCRIPTION (PBGA PACKAGE ONLY) Symbol Name I/O Description ASYR(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW WritePort willselectAsynchronousoperation. TCK(2) JTAGClock I ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAGTestData I OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata Input seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister. Aninternalpull-upresistorforcesTDIHIGHifleftunconnected. TDO(2) JTAGTestData O OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata Output seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode I TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected. TRST(2) JTAGReset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon power-up. If the JTAG function is not used then this signal should to be tied to GND. PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES) SEN SerialEnable I SENenablesserialloadingofprogrammableflagoffsets. WCLK/ WriteClock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK WR WriteStrobe writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdataintotheFIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of the WCLK/WR input is only available in the PBGA package. WEN WriteEnable I WEN enables WCLK for writing data into the FIFO memory and offset registers. VCC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail. Symbol Name I/O Description NOTE: 1. Inputs should not change state after Master Reset. |
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