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7007S20GGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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7007S20GGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 22 page  1 AUGUST 2014 DSC 2940/14 ©2014 Integrated Device Technology, Inc. I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A14L A0L 2940 drw 01 I/O0L-I/O7L CEL OEL R/ WL SEML INTL M/ S BUSYR I/O0R-I/O7R A14R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER R/ WR 15 15 HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM ◆ True Dual-Ported memory cells which allow simulta- neous reads of the same memory location ◆ High-speed access – Military: 25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) – Commercial: 15/20/25/35/55ns (max.) ◆ Low-power operation – IDT7007S Active: 850mW (typ.) Standby: 5mW (typ.) – IDT7007L Active: 850mW (typ.) Standby: 1mW (typ.) ◆ IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave ◆ Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible, single 5V (±10%) power supply ◆ Available in 68-pin PGA and PLCC and a 80-pin TQFP ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. Functional Block Diagram IDT7007S/L Features |
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