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70V27L20BFGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V27L20BFGI Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 21 page ©2012 Integrated Device Technology, Inc. 6.01 1 SEPTEMBER 2012 DSC3603/12 Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/35ns (max.) ◆ Low-power operation – IDT70V27S Active: 500mW (typ.) Standby: 3.3mW (typ.) – IDT70V27L Active: 500mW (typ.) Standby: 660 µW (typ.) ◆ Separate upper-byte and lower-byte control for bus matching capability ◆ Dual chip enables allow for depth expansion without external logic IDT70V27S/L ◆ IDT70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ LVTTL-compatible, single 3.3V (±0.3V) power supply ◆ Available in 100-pin Thin Quad Flatpack (TQFP), and 144- pin Fine Pitch BGA (fpBGA) ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information I/O Control Address Decoder 32Kx16 MEMORY ARRAY 70V27 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ WL A14L A0L A14L A0L SEML INT L (2) BUSYL (1,2) LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/ WR A14R A0R A14R A0R SEMR INTR (2) BUSYR (1,2) LBR R/ WR OER UBR M/ S (2) CE1L CE0R CE1R 3603 drw 01 I/O0-7L CE1R CE1L I/O8-15L I/O0-7R I/O8-15R R/ WL , NOTES: 1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2) BUSY and INT are non-tri-state totem-pole outputs (push-pull). HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM Functional Block Diagram |
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