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72V271LA10TFGI Datasheet(PDF) 2 Page - Integrated Device Technology

Part # 72V271LA10TFGI
Description  3.3 VOLT CMOS SuperSync FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

72V271LA10TFGI Datasheet(HTML) 2 Page - Integrated Device Technology

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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
2
PIN CONFIGURATIONS
TQFP (PN64, ORDER CODE: PF)
STQFP (PP64, ORDER CODE: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC(1)
VCC
VCC
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
Q7
Q6
GND
4673 drw 02
write controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the
other has been removed. The Frequency Select pin (FS) has been
removed, thus it is no longer necessary to select which of the two clock
inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short.
(The variable clock cycle counting delay associated with the latency
period found on previous SuperSync devices has been eliminated on
this SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, tele-
communications, data communications and other applications that need to
buffer large amounts of data.
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output
Enable (OE) input is provided for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from
0 to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.


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