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72V205L20TFG Datasheet(PDF) 10 Page - Integrated Device Technology |
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72V205L20TFG Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 25 page  10 IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES MARCH 2013 When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; thenasignalatthisinputcanneitherincrementthewriteoffsetregisterpointer, nor execute a write. The contents of the offset registers can be read on the output lines when theLDpinissetLOWandRENissetLOW;then,datacanbereadontheLOW- to-HIGH transition of the Read Clock (RCLK). The act of reading the control registersemploysadedicatedreadoffsetregisterpointer.(Thereadandwrite pointersoperateindependently). Offsetregistercontentcanbereadoutinthe IDT Standard mode only. It is inhibited in the FWFT mode. A read and a write should not be performed simultaneously to the offset registers. FIRST LOAD (FL) Forthesingledevicemode,seeTable3foradditionalinformation. Inthe DaisyChainDepthExpansionconfiguration,FLisgroundedtoindicateitisthe firstdeviceloadedandissettoHIGHforallotherdevicesintheDaisyChain. (SeeOperatingConfigurationsforfurtherdetails.) WRITE EXPANSION INPUT (WXI) This is a dual purpose pin. For single device mode, see Table 3 for additionalinformation. WXIisconnectedtoWriteExpansionOut(WXO)ofthe previous device in the Daisy Chain Depth Expansion mode. READ EXPANSION INPUT (RXI) This is a dual purpose pin. For single device mode, see Table 3 for additionalinformation.RXIisconnectedtoReadExpansionOut(RXO)ofthe previous device in the Daisy Chain Depth Expansion mode. OUTPUTS: FULL FLAG/INPUT READY (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) functionisselected.WhentheFIFOisfull,FFwillgoLOW,inhibitingfurtherwrite operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed afterareset,FF willgoLOWafterDwritestotheFIFO. D=256writesforthe IDT72V205,512fortheIDT72V215,1,024fortheIDT72V225,2,048forthe IDT72V235 and 4,096 for the IDT72V245. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW whenmemoryspaceisavailableforwritingindata. When thereisnolonger any free space left, IR goes HIGH, inhibiting further write operations. IRwillgoHIGHafterDwritestotheFIFO. D=257writesfortheIDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. FF/IR is synchronous and updated on the rising edge of WCLK. EMPTYFLAG/OUTPUTREADY(EF/OR) Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF) functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther read operations. When EF is HIGH, the FIFO is not empty. InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs, indicating the last word was read. Further data reads are inhibited until OR goesLOWagain. EF/OR is synchronous and updated on the rising edge of RCLK. PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full Flag (PAF) will go LOW when FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after Reset (RS), the PAF will go LOW after (256-m) writes for the IDT72V205, (512-m) writes for the IDT72V215, (1,024-m) writes for the IDT72V225,(2,048–m)writesfortheIDT72V235and(4,096–m)writesforthe IDT72V245. The offset “m” is defined in the Full Offset register. In FWFT mode, if no reads are performed, PAF will go LOW after 257-m fortheIDT72V205,513-mfortheIDT72V215,1,025fortheIDT72V225,2,049 fortheIDT72V235and4,097fortheIDT72V245.Thedefaultvaluesformare noted in Table 1 and 2. IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).IfsynchronousPAF configurationisselected(seeTable3),thePAFisupdatedontherisingedge ofWCLK. PROGRAMMABLEALMOST-EMPTYFLAG(PAE) The PAE flag will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words orlessintheFIFO. InFWFTmode,thePAEwillgoLOWwhentherearen + 1 wordsorlessintheFIFO.Theoffset"n"isdefinedastheemptyoffset. Thedefault values for n are noted in Table 1 and 2. Ifthereisnoemptyoffsetspecified,theProgrammableAlmost-EmptyFlag (PAE) will be LOW when the device is 31 away from completely empty for IDT72V205, 63 away from completely empty for IDT72V215, and 127 away fromcompletelyemptyforIDT72V225/72V235/72V245. IfasynchronousPAEconfigurationisselected,thePAEisassertedLOWon theLOW-to-HIGHtransitionoftheReadClock(RCLK).PAEisresettoHIGH ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).IfsynchronousPAE configurationisselected(seeTable3),the PAEisupdatedontherisingedge of RCLK. WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXI) and/or Read Expansion In (RXI) are grounded,thisoutputactsasanindicationofahalf-fullmemory. Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is asynchronous. In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of thepreviousdevice. ThisoutputactsasasignaltothenextdeviceintheDaisy Chainbyprovidingapulsewhenthepreviousdevicewritestothelastlocation ofmemory. READ EXPANSION OUT (RXO) In the Daisy Chain Depth Expansion configuration, Read Expansion In (RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse when the previous device reads from the last location of memory. DATAOUTPUTS(Q0-Q17) Q0-Q17 are data outputs for 18-bit wide data. |
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