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71V30L35TFG Datasheet(PDF) 10 Page - Integrated Device Technology |
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71V30L35TFG Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 15 page 6.42 IDT71V30S/L High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 10 NOTES: 1. tWH must be met for BUSY. 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Timing Waveform of BUSY Arbitration Controlled Address Match Timing(1) Timing Waveform of Write with BUSY(3) Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. BUSY'B' 3741 drw 11 R/ W'A' tWP tWH tWB R/ W'B' (2) (1) , tAPS ADDR 'A' AND 'B' ADDRESSES MATCH tBAC tBDC CE'B' CE'A' BUSY'A' 3741 drw 12 (2) BUSY'B' ADDRESSES DO NOT MATCH ADDRESSES MATCH tAPS ADDR'A' ADDR'B' tRC OR tWC 3741 drw 13 (2) tBAA tBDA |
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