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70V08L15PFG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V08L15PFG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 21 page  ©2015 Integrated Device Technology, Inc. 1 FEBRUARY 2015 DSC-3740/9 I/O Control Address Decoder 64Kx8 MEMORY ARRAY 70V08 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE 0L OEL R/ W L A15L A0L I/O 0-7L A15L A 0L SEML I NTL (2) BUSYL (1,2) R/ W L CE0L OEL I/O Control Address Decoder OE R R/ WR CE0R A15R A 0R A15R A 0R I/O 0-7R SEMR INT R (2) R BUSY (1,2) M/ S (1) CE1L R/ WR CE0R OER CE1R 3740 drw 01 1L CE 1R CE Functional Block Diagram ◆ ◆ ◆ ◆ ◆ IDT70V08 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in a 100-pin TQFP ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 15/20/25/35ns (max.) – Industrial: 20ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V08S Active: 550mW (typ.) Standby: 5mW (typ.) – IDT70V08L Active: 550mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic HIGH-SPEED 3.3V 64K x 8 DUAL-PORT STATIC RAM IDT70V08S/L NOTES: 1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). |
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