9

IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18, 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Figure 4. Programmable Flag Offset Programming Sequence

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 3. Offset Register Location and Default Values

EMPTY OFFSET REGISTER

17

0

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

12

12

IDT72V255LA

⎯ 8,192 x 18 - BIT

4672 drw 06

EMPTY OFFSET REGISTER

17

0

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

FULL OFFSET REGISTER

17

0

DEFAULT VALUE

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

13

13

IDT72V265LA

⎯ 16,384 x 18 - BIT

Selection

Parallel write to registers:

Empty Offset

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

No Operation

Write Memory

Read Memory

No Operation

4672 drw 07

LD

0

0

X

1

1

1

0

WEN

0

1

1

0

X

1

1

REN

1

0

1

X

0

1

1

Serial shift into registers:

26 bits for the 72V255LA

28 bits for the 72V265LA

SEN

1

1

1

X

X

X

0

WCLK

X

X

X

X

RCLK

X

X

X

X

X

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)