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72V285L20PFGI8 Datasheet(PDF) 10 Page - Integrated Device Technology |
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72V285L20PFGI8 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 25 page 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM 32,768 x 18 and 65,536 x 18 SERIAL PROGRAMMING MODE IfSerialProgrammingmodehasbeenselected,asdescribedabove,then programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK and SI input pins. Programming PAE andPAFproceedsasfollows: whenLDandSENaresetLOW,dataonthe SIinputarewritten,onebitforeachWCLKrisingedge,startingwiththeEmpty Offset LSB and ending with the Full Offset MSB. A total of 30 bits for the IDT72V275 and 32 bits for the IDT72V285. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode. Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoes nothavetooccuratonce. AselectnumberofbitscanbewrittentotheSIinput andthen,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restoredtoaLOW,thenextoffsetbitinsequenceiswrittentotheregistersvia SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. Once LD and SEN are both restored to a LOW level, serial offset programming continues. Fromthetimeserialprogramminghasbegun,neitherpartialflagwillbevalid until the full set of bits required to fill all the offset registers has been written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. It is not possible to read the flag offset values in a serial mode. PARALLELMODE IfParallelProgrammingmodehasbeenselected,asdescribedabove,then programming of PAE and PAF values can be achieved by using a combinationoftheLD, WCLK,WENandDninputpins. ProgrammingPAE and PAF proceeds as follows: when LD and WEN are set LOW, data on theinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGH transitionofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,data arewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,once again, to the Empty Offset Register. See Figure 14, Parallel Loading of Programmable Flag Registers, for the timing diagram for this mode. Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister pointer. The act of reading offsets employs a dedicated read offset register pointer.Thetwopointersoperateindependently;however,areadandawrite shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas noeffectonthepositionofthesepointers. Write operations to the FIFO are allowed before and during the parallel programmingsequence.Inthiscase,theprogrammingofalloffsetregisters does not have to occur at one time. One, two or more offset registers can be written and then by bringing LD HIGH, write operations can be redirected to the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offsetregisterinsequenceiswrittento.AsanalternativetoholdingWENLOW andtogglingLD,parallelprogrammingcanalsobeinterruptedbysetting LD LOWandtogglingWEN. Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduring theprogrammingprocess. Fromthetimeparallelprogramminghasbegun,a partial flag output will not be valid until the appropriate offset word has been writtentotheregister(s)pertainingtothatflag.MeasuringfromtherisingWCLK edge that achieves the above criteria; PAFwillbevalidaftertwomorerising WCLKedgesplustPAF,PAEwillbevalidafterthenexttworisingRCLKedges plus tPAE plus tSKEW2. The act of reading the offset registers employs a dedicated read offset registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn pinswhenLDissetLOWandRENissetLOW.DataarereadviaQnfromthe EmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthe second LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register. ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffset Register.SeeFigure15, ParallelReadofProgrammableFlagRegisters, for thetimingdiagramforthismode. Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD, or both together. When REN and LD are restored to a LOW level, reading oftheoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed, the data word that was present on the output lines Qn will be overwritten. Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected. RETRANSMITOPERATION The Retransmit operation allows data that has already been read to be accessedagain. Therearetwostages:first,asetupprocedurethatresetsthe read pointer to the first location of memory, then the actual retransmit, which consistsofreadingoutthememorycontents,startingatthebeginningofmemory. RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge. REN and WEN must be HIGH before bringing RT LOW. Atleastoneword, butnomorethanD-2words should have been written into the FIFO between Reset(MasterorPartial)andthetimeofRetransmitsetup. D = 32,768forthe IDT72V275 and D = 65,536 for the IDT72V285. In FWFT mode, D = 32,769 for the IDT72V275 and D= 65,537 for the IDT72V285. If IDT Standard mode is selected, the FIFO will mark the beginning of the RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable if EF was HIGH before setup. During this period, the internal read pointer is initializedtothefirstlocationoftheRAMarray. WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant timing diagram. IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit setupbysetting ORHIGH.Duringthisperiod,theinternalreadpointerisset to the first location of the RAM array. WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected, thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading all subsequent words requires a LOW on REN to enable the rising edge of RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming diagram. ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HF and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,thePAEflagwillbeupdated. HFisasynchronous,thustherisingedge ofRCLKthatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thus thesecondrisingedgeofWCLKthatoccurstSKEWaftertherisingedgeofRCLK that RT is setup will update PAF. RT is synchronized to RCLK. |
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