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72V291L15PFGI8 Datasheet(PDF) 9 Page - Integrated Device Technology |
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72V291L15PFGI8 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 26 page 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 and 131,072 x 9 Figure 4. Programmable Flag Offset Programming Sequence Figure 3. Offset Register Location and Default Values NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. WCLK RCLK X X XX X X XX 4513 drw 07 LD 0 0 X 1 1 1 0 WEN 0 1 1 0 X 1 1 REN 1 0 1 X 0 1 1 X SEN 1 1 1 X X X 0 Parallel write to registers: Empty Offset (LSB) Full Offset (LSB) Full Offset (MSB) Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Memory Read Memory No Operation Empty Offset (MSB) Serial shift into registers: 32 bits for the 72V281 Full Offset (LSB) Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Memory Read Memory No Operation Serial shift into registers: Empty Offset (Mid-Byte) Full Offset (Mid-Byte) 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) Parallel write to registers: Empty Offset (LSB) Full Offset (MSB) Full Offset (Mid-Byte) Empty Offset (Mid-Byte) Empty Offset (MSB) 34 bits for the 72V291 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) 72V281 72V291 EMPTY OFFSET (LSB) REGISTER 87 0 72V281 (65,536 x 9›BIT) FULL OFFSET (LSB) REGISTER 8 7 0 FULL OFFSET (MSB) REGISTER 87 0 DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset EMPTY OFFSET (MSB) REGISTER 87 0 DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset EMPTY OFFSET (LSB) REGISTER 87 0 72V291 (131,072 x 9›BIT) FULL OFFSET (LSB) REGISTER 87 0 FULL OFFSET (MID-BYTE) REGISTER 8 7 0 DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset EMPTY OFFSET (MID-BYTE) REGISTER 87 0 DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset 81 0 0H 80 1 DEFAULT 0H DEFAULT EMPTY OFFSET (MSB) REGISTER FULL OFFSET (MSB) REGISTER 4513 drw 06 |
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