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72V291L10PFGI8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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72V291L10PFGI8 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 26 page 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 and 131,072 x 9 Number of Words in FIFO 0 1 to n (1) 0 1 to n (1) (n+1) to 32,768 32,769 to (65,536-(m+1)) (65,536-m) (2) to 65,535 65,536 72V281 72V291 FF PAF HF PAE EF HH HL L HH HL H HH H H H HH L H H HL L H H LL LH H 4513 drw 05 0 1 to n+1(1) 0 1 to n+1(1) (n+2) to 65,537 65,538 to (131,073-(m+1)) (131,073-m) (2) to 131,072 131,073 IR PAF HF PAE OR LH H L H LH H L L L H HHL LH L H L LLL H L HL L H L 72V281 72V291 Number of Words in FIFO (n+1) to 65,536 65,537 to (131,072-(m+1)) (131,072-m) (2) to 131,071 131,072 (n+2) to 32,769 32,770 to (65,537-(m+1)) (65,537-m) (2) to 65,536 65,537 NOTES: 1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected. 2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected. NOTES: 1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected. 2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected. In addition to loading offset values into the FIFO, it also possible to read the current offset values. It is only possible to read offset values via parallel read. Figure 4, Programmable Flag Offset Programming Sequence, summa- rizes the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. TABLE 1 ⎯ STATUS FLAGS FOR IDT STANDARD MODE TABLE 2 ⎯ STATUS FLAGS FOR FWFT MODE |
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