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72V275L15TFG Datasheet(PDF) 2 Page - Integrated Device Technology |
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72V275L15TFG Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 25 page 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM 32,768 x 18 and 65,536 x 18 PIN CONFIGURATIONS TQFP (PN64, order code: PF) STQFP (PP64, order code: TF) TOP VIEW DESCRIPTION (Continued) PIN 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 WEN SEN DC(1) VCC GND D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q17 Q16 GND Q15 Q14 VCC Q13 Q12 Q11 GND Q10 Q9 Q8 Q7 Q6 GND 4512 drw 02 TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable (WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input and Read Enable (REN) input. Data is read from the FIFO on every rising edgeofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovided forthree-statecontroloftheoutputs. ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. In FWFT mode, the first word written to an empty FIFO is clocked directly tothedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoes not have to be asserted for accessing the first word. However, subsequent wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding data inputs of the next). No external logic is required. NOTE: 1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open. |
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