 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
72V2111L20PFG8 Datasheet(PDF) 11 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
72V2111L20PFG8 Datasheet(HTML) 11 Page - Integrated Device Technology |
|
|
11 / 27 page  11 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds as follows: when LD and SEN are set LOW, data on the SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 36 bits for the IDT72V2101 and 38 bits for the IDT72V2111. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode. Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN HIGH, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored to a LOW, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level, serial offset programming continues. From the time serial programming has begun, neither partial flag will be valid until the full set of bits required to fill all the offset registers has been written. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. It is not possible to read the flag offset values in a serial mode. PARALLEL MODE IfParallelProgrammingmodehasbeenselected,asdescribedabove,then programmingofPAEandPAFvaluescanbeachievedbyusingacombination of the LD, WCLK , WEN and Dn input pins. ProgrammingPAEandPAFproceedsasfollows: whenLDandWENare setLOW,dataontheinputsDnarewrittenintotheEmptyOffsetLSBRegister onthefirstLOW-to-HIGHtransitionofWCLK. UponthesecondLOW-to-HIGH transitionofWCLK,dataarewrittenintotheEmptyOffsetMid-ByteRegister. UponthethirdLOW-to-HIGHtransitionofWCLK,data arewrittenintotheEmpty OffsetMSBRegister. UponthefourthLOW-to-HIGHtransitionofWCLK,data are written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH transitionofWCLK,dataarewrittenintotheFullOffsetMid-ByteRegister. Upon thesixthLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffset MSB Register. The seventh transition of WCLK writes, once again, into the EmptyOffsetLSBRegister.SeeFigure14,ParallelLoadingofProgrammable FlagRegisters,forthetimingdiagramforthismode. Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister pointer. The act of reading offsets employs a dedicated read offset register pointer.Thetwopointersoperateindependently;however,areadandawrite shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas noeffectonthepositionofthesepointers. Write operations to the FIFO are allowed before and during the parallel programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling LD, parallel programming can also be interrupted by setting LD LOW and togglingWEN. Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduringthe programmingprocess. Fromthetimeparallelprogramminghasbegun,apartial flagoutputwillnotbevaliduntiltheappropriateoffsetwordhasbeenwrittento theregister(s)pertainingtothatflag.MeasuringfromtherisingWCLKedgethat achievestheabovecriteria;PAFwillbevalidaftertwomorerisingWCLKedges plustPAF,PAEwillbevalidafterthenexttworisingRCLKedgesplustPAEplus tSKEW2. The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q0- Qn pins when LD is set LOW and REN is set LOW. For the IDT72V2101/72V2111, data is read via Qn from the Empty Offset LSB Register on the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGHtransitionofRCLK, dataarereadfromtheEmptyOffsetMid-Byte Register. UponthethirdLOW-to-HIGHtransitionofRCLK,dataarereadfrom the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset LSB Register. Upon the fifth LOW- to-HIGHtransitionofRCLK,dataarereadfromtheFullOffsetMid-ByteRegister. Upon the sixth LOW-to-HIGH transition of RCLK, data are read from the Full OffsetMSBRegister. TheseventhtransitionofRCLKreads,onceagain,from theEmptyOffsetLSBRegister.SeeFigure15,ParallelReadofProgrammable Flag Registers, for the timing diagram for this mode. Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD, or both together. When REN and LD are restored to a LOW level, reading of theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed, the data word that was present on the output lines Qn will be overwritten. Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected. RETRANSMITOPERATION The Retransmit operation allows data that has already been read to be accessed again. There are two stages: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. At least two words, but no more than D - 2 words should have been written into the FIFO and read from the FIFO between Reset (Master or Partial) and the time of Retransmitsetup. D = 262,144fortheIDT72V2101andD = 524,288forthe IDT72V2111 in IDT Standard mode. In FWFT mode, D = 262,145 for the IDT72V2101 and D = 524,289 for the IDT72V2111. If IDT Standard mode is selected, the FIFO will mark the beginning of the RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable if EF was HIGH before setup. During this period, the internal read pointer is initializedtothefirstlocationoftheRAMarray. |
Similar Part No. - 72V2111L20PFG8 |
|
Similar Description - 72V2111L20PFG8 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
