6.42

IDT71V30S/L

High-Speed 1K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

9

MATCH

VALID

MATCH

VALID

3741 drw 10

(1)

R/

NOTES:

1. To ensure that the earlier of the two ports wins.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

AC Electrical Characteristics Over the

NOTES:

1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".

2. To ensure that the earlier of the two ports wins.

4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.

5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.

6. 'X' in part number indicates power rating (S or L).

7. Industrial temperature: for specific speeds, packages and powers contact your sales office.

71V30X25

Com'l Only

71V30X35

Com'l & Ind

71V30X55

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

BUSY

BUSY

Access Time from Address Match

____

20

____

20

____

30

ns

BUSY

Disable Time from Address Not Matched

____

20

____

20

____

30

ns

BUSY

Access Time from Chip Enable

____

20

____

20

____

30

ns

BUSY

Disable Time from Chip Enable

____

20

____

20

____

30

ns

20

____

30

____

40

____

ns

____

50

____

60

____

80

ns

____

35

____

45

____

65

ns

5

____

5

____

5

____

ns

BUSY

____

30

____

30

____

45

ns

3741 tbl 11