Commercial and Industrial Temperature Range

IDT 70V27S/L

High-Speed 3.3V 32K x 16 Dual-Port Static RAM

11

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

10. Refer to Chip Enable Truth Table.

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

UB or LB

3603 drw 07

(9)

CE or SEM

(9,10)

(7)

(3)

3603 drw 08

ADDRESS

R/

W

UB or LB

(3)

(2)

(6)

CE or SEM

(9,10)

(9)