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71V30S55TFGI8 Datasheet(PDF) 4 Page - Integrated Device Technology |
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71V30S55TFGI8 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 15 page 6.42 IDT71V30S/L High-Speed 1K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 4 NOTES: 1. VCC = 2V, TA = +25°C, and is not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but not production tested. Data Retention Characteristics (L Version Only) DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V) NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.) 3. At f = fMAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to chip enable Truth Table I. 7. Industrial temperature: for specific speeds, packages and powers contact your sales office. Symbol Parameter Test Condition 71V30L Unit Min. Typ.(1) Max. VDR VCC for Data Retention 2.0 ____ ____ V ICCDR Data Retention Current VCC = 2V, CE > VCC -0.2V Ind. ____ 100 1000 µA Com'l. ____ 100 500 tCDR(3) Chip Deselect to Data Retention Time VIN > VCC -0.2V or VIN < 0.2V 0 ____ ____ ns tR(3) Operation Recovery Time tRC(2) ____ ____ ns 3741 tbl 07 Symbol Parameter Test Condition Version 71V30X25 Com'l Only 71V30X35 Com'l & Ind 71V30X55 Com'l Only Unit Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. ICC Dynamic Operating Current (Both Ports Active) CEL and CER = VIL, Outputs Disabled f = fMAX(3) COM'L S L 75 75 150 120 75 75 145 115 75 75 135 105 mA IND S L ___ ___ ___ ___ ___ 75 ___ 145 ___ ___ ___ ___ ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER= VIL, f = fMAX(3) COM'L S L 20 20 50 35 20 20 50 35 20 20 50 35 mA IND S L ___ ___ ___ ___ ___ 20 ___ 50 ___ ___ ___ ___ ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) COM'L S L 30 30 105 75 30 30 100 70 30 30 90 60 mA IND S L ___ ___ ___ ___ ___ 30 ___ 100 ___ ___ ___ ___ ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) COM'L S L 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 mA IND S L ___ ___ ___ ___ ___ 1.0 ___ 5.0 ___ ___ ___ ___ ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f=fMAX(3) COM'L S L 30 30 90 75 30 30 85 70 30 30 75 60 mA IND S L ___ ___ ___ ___ ___ 30 ___ 85 ___ ___ ___ ___ 3741 tbl 06 |
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