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70V37L15PFGI8 Datasheet(PDF) 4 Page - Integrated Device Technology |
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70V37L15PFGI8 Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 17 page  6.42 IDT70V37L High-Speed 3.3V 32K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 4 Truth Table III – Semaphore Read/Write Control(1) Truth Table I – Chip Enable(1,2) NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only. 2. 'H' = VIH and 'L' = VIL. 3. CMOS standby requires 'X' to be either < 0.2V or >VDD-0.2V. Truth Table II – Non-Contention Read/Write Control NOTES: 1. A0L — A14L ≠ A0R — A14R 2. Refer to Truth Table I - Chip Enable. NOTES: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2. 2. Refer to Truth Table I - Chip Enable. CE CE0 CE1 Mode L VIL VIH Port Selected (TTL Active) < 0.2V >VDD -0.2V Port Selected (CMOS Active) H VIH X Port Deselected (TTL Inactive) XVIL Port Deselected (TTL Inactive) >VDD -0.2V X(3) Port Deselected (CMOS Inactive) X(3) <0.2V Port Deselected (CMOS Inactive) 4852 tbl 06 Inputs(1) Outputs Mode CE(2) R/W OE UB LB SEM I/O9-17 I/O0-8 H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected LL X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only LL X L L H DATAIN DATAIN Write to Both Bytes LH L L H H DATAOUT High-Z Read Upper Byte Only L H LH LH High-Z DATAOUT Read Lower Byte Only LH L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 4851 tbl 07 Inputs(1) Outputs Mode CE(2) R/W OE UB LB SEM I/O9-17 I/O0-8 HH L X X L DATAOUT DATAOUT Read Data in Semaphore Flag XH L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H ↑ XXX L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ XH H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X XL XL ______ ______ Not Allowed L XXX L L ______ ______ Not Allowed 4851 tbl 08 |
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