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72V275L10TFG8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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72V275L10TFG8 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 25 page 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM 32,768 x 18 and 65,536 x 18 Number of Words in FIFO 0 1 to n (1) (n+1) to 16,384 16,385 to (32,768-(m+1)) (32,768-m) (2) to 32,767 32,768 0 1 to n (1) (n+1) to 32,768 32,769 to (65,536-(m+1)) (65,536-m) (2) to 65,535 65,536 TABLE 2. STATUS FLAGS FOR FWFT MODE 72V275 72V285 FF PAF HF PAE EF HH HL L HH HL H HH H H H HH L H H HL L H H LL LH H TABLE 1. STATUS FLAGS FOR IDT STANDARD MODE 4512 drw 05 0 1 to n+1(1) (n+2) to 16,385 (32,769-m) (2) to 32,768 32,769 0 1 to n+1(1) (n+2) to 32,769 32,770 to (65,537-(m+1)) (65,537-m) (2) to 65,536 65,537 IR PAF HF PAE OR LH H L H LH H L L L H HHL LH L H L LLL H L HL L H L 72V275 72V285 Number of Words in FIFO 16,386 to (32,769-(m+1)) NOTES: 1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected. 2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected. NOTES: 1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected. 2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected. Figure 4, Programmable Flag Offset Programming Sequence, summa- rizes the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen selected. |
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