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72T36135ML5BBGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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72T36135ML5BBGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 48 page  1 MAY 2016 DSC-6723/5 © 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 2.5V 18M-BIT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 524,288 x 36 IDT72T36135M IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEATURES: ••••• Industry’s largest FIFO memory organization: IDT72T36135 ⎯ ⎯ ⎯ ⎯ ⎯ 524,288 x 36 - 18M-bits ••••• Up to 200 MHz Operation of Clocks ••••• Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync devices ••••• User selectable HSTL/LVTTL Input and/or Output ••••• User selectable Asynchronous read and/or write port timing ••••• Mark & Retransmit, resets read pointer to user marked position ••••• Write Chip Select (WCS) input disables Write Port ••••• Read Chip Select (RCS) synchronous to RCLK ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets ••••• Program programmable flags by either serial or parallel means ••••• Selectable synchronous/asynchronous timing modes for Almost- Empty and Almost-Full flags ••••• Separate SCLK input for Serial programming of flag offsets ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Empty and Full flags signal FIFO status ••••• Select IDT Standard timing (using EF[1:2] and FF[1:2] flags) or First Word Fall Through timing (using OR[1:2] and IR[1:2] flags) ••••• Output enable puts data outputs into high impedance state ••••• JTAG port, provided for Boundary Scan function ••••• Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) 50% more space saving than the leading 9M-bit FIFOs ••••• Independent Read and Write Clocks (permit reading and writing simultaneously) ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available ••••• Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 524,288 x 36 FLAG LOGIC FF/IR[1:2] PAF[1:2] EF/OR[1:2] PAE[1:2] READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK/WR D0 -Dn (x36) LD MRS REN RCLK/RD OE Q0 -Qn (x36) OFFSET REGISTER PRS FWFT/SI SEN RT 6723 drw01 PFM FSEL0 FSEL1 MARK SCLK RCS JTAG CONTROL (BOUNDARY SCAN) TCK TMS TDO TDI TRST ASYR WCS HSTL I/0 CONTROL Vref WHSTL RHSTL ASYW SHSTL |
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