DT72T7295 datasheet(8/53 Pages) IDT

Part #	DT72T7295

Description	2.5 VOLT HIGH-SPEED TeraSync FIFO 72-BIT CONFIGURATIONS

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Manufacturer	IDT [Integrated Device Technology]

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync

™

™ 72-BIT FIFO

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

TRST(2)

JTAG Reset

HSTL-LVTTL

TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically

INPUT

reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG

function is used but the user does not want to use

TRST, then TRST can be tied with MRS to ensure proper

FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

WEN

WriteEnable

HSTL-LVTTL When Synchronous operation of the write port has been selected,

WEN enables WCLK for writing data into

INPUT

the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the

WEN input should be tied LOW.

WCS

WriteChipSelect

HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This

INPUT

provides added power savings.

WCLK/

WriteClock/

HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by

WEN,therisingedgeofWCLK

WR

WriteStrobe

INPUT

writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into

the FIFO on a rising edge in an Asynchronous manner, (

WEN should be tied to its active state).

WHSTL(1) Write Port HSTL

LVTTL

This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must

Select

INPUT

be tied HIGH. Otherwise it should be tied LOW.

VCC

+2.5v Supply

I

These are Vcc supply inputs and must be connected to the 2.5V supply rail.

GND

Ground Pin

I

These are Ground pins and must be connected to the GND rail.

Vref

Reference

I

This is a Voltage Reference input and must be connected to a voltage level determined from the table,

Voltage

“Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class

inputs. If HSTL class inputs are not being used, this pin should be tied LOW.

VDDQ

O/P Rail Voltage

I

This pin should be tied to the desired voltage rail for providing power to the output drivers.

PIN DESCRIPTION (CONTINUED)

Symbol

Name

I/O TYPE

Description

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 29-31 and Figures 6-8.

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