Electronic Components Datasheet Search |
|
72V275L20TFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
72V275L20TFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 25 page 1 OCTOBER 2014 3.3 VOLT CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18 IDT72V275 IDT72V285 ©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES DSC-4512/4 FEATURES: ••••• Choose among the following memory organizations: IDT72V275 32,768 x 18 IDT72V285 65,536 x 18 ••••• Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs ••••• 10ns read/write cycle time (6.5ns access time) ••••• Fixed, low first word data latency time ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Retransmit operation with fixed, low first word data latency time ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets ••••• Program partial flags by either serial or parallel means ••••• Select IDT Standard timing (using EF EF EF EF EF and FF FF FF FF FF flags) or First Word Fall Through timing (using OR OR OR OR OR and IR IR IR IR IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• Independent Read and Write clocks (permit reading and writing simultaneously) ••••• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin Slim Thin Quad Flat Pack (STQFP) ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (-40°C to +85°C) is available ••••• Green parts are available, see ordering information DESCRIPTION: The IDT72V275/72V285 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK or WCLK, is running at the higher frequency. • The period required by the retransmit operation is now fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyncfamily.) SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom- munications,datacommunicationsandotherapplicationsthatneedtobuffer largeamountsofdata. FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 32,768 x 18 65,536 x 18 FLAG LOGIC FF/IR PAF EF/OR PAE HF READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC WEN WCLK D0 -D17 LD MRS REN RCLK OE Q0 -Q17 OFFSET REGISTER PRS FWFT/SI SEN RT 4512 drw 01 |
Similar Part No. - 72V275L20TFGI8 |
|
Similar Description - 72V275L20TFGI8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |