 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT72V2101 Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT72V2101 Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 27 page  3 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9 Figure 1. Block Diagram of Single 262,144 x 9 and 524,288 x 9 Synchronous FIFO PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127 or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith the LD pin during Master Reset. For serial programming, SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite pointers are set to the first location of the FIFO. The FWFT pin selects IDT StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023 withserialprogramming. Theflagsareupdatedaccordingtothetimingmode anddefaultoffsetsselected. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, partial flag program- ming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid- operation, when reprogramming partial flags would be undesirable. The Retransmit function allows data to be reread from the FIFO. A LOW on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. The IDT72V2101/72V2111 are fabricated using IDT’s high speed submi- cron CMOS technology. DATA OUT (Q0 - Qn) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72V2101 72V2111 PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 4669 drw 03 HALF FULL FLAG ( HF) SERIAL ENABLE( SEN) |
Similar Part No. - IDT72V2101_14 |
|
Similar Description - IDT72V2101_14 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
