IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

7

Number of Words in FIFO

IDT72V805

IDT72V815

IDT72V825

IDT72V835

IDT72V845

IR PAF HF PAE OR

00

0

0

0

L

H

H

L

H

LH

HL

L

(n + 2) to 129

(n + 2) to 257

(n + 2) to 513

(n + 2) to 1,025

(n + 2) to 2,049

L

H

H

H

L

LHLHL

(257-m) to 256

(513-m) to 512

(1,025-m) to 1,024

(2,049-m) to 2,048

(4,097-m) to 4,096

LL

L

H

L

257

513

1,025

2,049

4,097

H

L

L

H

L

normal read/write operation. When the LD pin and WEN are again set LOW,

the next offset register in sequence is written.

The contents of the offset registers can be read on the data output lines

Q0-Q11 when the LD pin is set LOW and REN is set LOW. Data can then

be read on the next LOW-to-HIGH transition of RCLK. The first transition

of RCLK will present the Empty Offset value to the data output lines. The

next transition of RCLK will present the Full Offset value. Offset register

content can be read out in the IDT Standard mode only. It cannot be read

in the FWFT mode.

SYNCHRONOUS VS ASYNCHRONOUS PROGRAMMABLE FLAG

TIMING SELECTION

The IDT72V805/72V815/72V825/72V835/72V845 can be configured

during the "Configuration at Reset" cycle described in Table 3 with either

asynchronous or synchronous timing for PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected (as per Table 3), the

PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset

to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is

asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset

to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-

grams, see Figure 13 for asynchronous PAE timing and Figure 14 for

asynchronous PAF timing.

If synchronous PAE/PAF configuration is selected , the PAE is asserted

and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF

is asserted and updated on the rising edge of WCLK only and not RCLK. For

detail timing diagrams, see Figure 22 for synchronous PAE timing and

Figure 23 for synchronous PAF timing.

REGISTER-BUFFERED FLAG OUTPUT SELECTION

The IDT72V805/72V815/72V825/72V835/72V845 can be configured

during the "Configuration at Reset" cycle described in Table 4 with single,

double or triple register-buffered flag output signals. The various combina-

tions available are described in Table 4 and Table 5. In general, going from

single to double or triple buffered flag outputs removes the possibility of

metastable flag indications on boundary states (i.e, empty or full condi-

tions). The trade-off is the addition of clock cycle delays for the respective

flag to be asserted. Not all combinations of register-buffered flag outputs

are supported. Register-buffered outputs apply to the Empty Flag and Full

Flag only. Partial flags are not effected. Table 4 and Table 5 summarize

the options available.

TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE

Number of Words in FIFO

IDT72V805

IDT72V815

IDT72V825

IDT72V835

IDT72V845

FF PAF HF PAE EF

00

0

0

0

H

H

H

L

L

HH

H

L

H

(n + 1) to 128

(n + 1) to 256

(n + 1) to 512

(n + 1) to 1,024

(n + 1) to 2,048

H

H

H

H

H

HH

L

H

H

(256-m) to 255

(512-m) to 511

(1,024-m) to 1,023

(2,048-m) to 2,047

(4,096-m) to 4,095

H

L

L

H

H

256

512

1,024

2,048

4,096

L

L

L

H

H

TABLE 2 — STATUS FLAGS FOR FWFT MODE

NOTES:

1. n = Empty Offset (Default Values : IDT72V805 n=31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)

2. m = Full Offset (Default Values : IDT72V805 m=31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)

NOTES:

1. n = Empty Offset (Default Values : IDT72V805 n = 31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)

2. m = Full Offset (Default Values : IDT72V805 m = 31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)